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Features
* Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV) * Access Time - 85 ns * Sector Erase Architecture * * *
- Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout - Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout Fast Word Program Time - 15 s Fast Sector Erase Time - 200 ms Suspend/Resume Feature for Erase and Program - Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Byte/Word by Suspending Programming of Any Other Byte/Word Low-power Operation - 25 mA Active - 10 A Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection VPP Pin for Write Protection RESET Input for Device Initialization Sector Lockdown Support TSOP, CBGA and BGA Package Options Top or Bottom Boot Block Configuration Available 128-bit Protection Register
* * * * * * * *
32-megabit (2M x 16/4M x 8) 3-volt Only Flash Memory AT49BV320 AT49BV320T AT49BV321 AT49BV321T AT49LV320 AT49LV320T AT49LV321 AT49LV321T
Recommend Using AT49BV320A(T)/322A(T) for New Designs.
Description
The AT49BV/LV32X(T) is a 3.0-volt 32-megabit Flash memor y organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 71 sectors for erase operations. The device is offered in 48-lead TSOP, and 48-ball CBGA and BGA packages. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming.
Pin Configurations
Pin Name A0 - A20 CE OE WE RESET RDY/BUSY VPP I/O0 - I/O14 I/O15 (A-1) BYTE NC VCCQ Function Addresses Chip Enable Output Enable Write Enable Reset READY/BUSY Output Write Protection Data Inputs/Outputs I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Selects Byte or Word Mode No Connect Output Power Supply
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1
TSOP Top View Type 1
A15 A14 A13 A12 A11 A10 A9 A8 NC A20 WE RESET VPP NC A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
BGA Top View (Ball Down)
1 A
A13 A11 A10 A12 I/O14 A8 WE A9 I/O5 I/O6 I/O13 I/O11 I/O12 I/O4 VPP RST A18 A20 I/O2 I/O3 VCC A19 A17 A6 I/O8 I/O9 I/O10 A7 A5 A3 CE I/O0 I/O1 A4 A2 A1 A0 GND OE
2
3
4
5
6
7
8
B
A14
C
AT49BV/LV320(T) AT49BV320(T)
A15
D
A16
E
VCCQ I/O15
F
GND I/O7
CBGA Top View (Ball Down) TSOP Top View Type 1
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET VPP NC RDY/BUSY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
1
2
3
4
5
6
A
A3 A7 A17 A6 A5 I/O0 I/O8 I/O9 I/O1 RDY/BUSY WE NC A18 A20 I/O2 I/O10 I/O11 I/O3 RST Vpp A19 I/O5 I/O12 VCC I/O4 A9 A8 A10 A11 I/O7 A13 A12 A14 A15 A16
B
A4
C
AT49BV/LV321(T)
A2
D
A1
E
A0
F
CE I/O14 BTYE I/O13 I/015/A-1 I/O6 VSS
G
OE
H
VSS
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AT49BV/LV320(T)/321(T)
The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see "Sector Lockdown" section). To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the toggle bit. The VPP pin provides data protection. When the V PP input is below 0.8V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to VCC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. When using the AT49BV/LV320(T) pinout configuration, the device always operates in the word mode. In the AT49BV/LV321(T) configuration, the BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic "1", the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic "0", the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tristated, and the I/O15 pin is used as an input for the LSB (A-1) address function.
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Block Diagram
I/O0 - I/O15/A-1
OUTPUT BUFFER
INPUT BUFFER
OUTPUT MULTIPLEXER
A0 - A20
INPUT BUFFER
DATA REGISTER
IDENTIFIER REGISTER
STATUS REGISTER
COMMAND REGISTER
ADDRESS LATCH DATA COMPARATOR
CE WE OE RESET BYTE
RDY/BUSY WRITE STATE MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE VOLTAGE SWITCH
VPP
VCC GND X-DECODER
MAIN MEMORY
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AT49BV/LV320(T)/321(T)
Device Operation
READ: The AT49BV/LV32X(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the "Command Definition in Hex" table on page 12 (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71 sectors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is tSEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating in 2 s. BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical "0") on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tBP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. If the erase/program status bit is a "1", the device was not able to verify that the erase or program operation was performed successfully.
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VPP PIN: The circuitry of the AT49BV/LV32X(T) is designed so that the device cannot be programmed or erased if the VPP voltage is less that 0.8V. When VPP is at 1.65V or above, normal program and erase operations can be performed. The Vpp pin cannot be left floating. PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The "Status Bit Table" on page 11 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the AT49BV/LV32X(T) contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, "00" or "01". If the configuration register is set to "00", the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a "01", a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a "00" or to a "01", any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is "00". Using the four-bus cycle Set Configuration Register command as shown in the "Command Definition in Hex" table on page 12, the value of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below. DATA POLLING: The AT49BV/LV32X(T) features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a "00", during a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see "Status Bit Table" on page 11 for more details. If the status bit configuration register is set to a "01", the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 1 and 2 on page 9. TOGGLE BIT: In addition to Data Polling the AT49BV/LV32X(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see "Status Bit Table" on page 11 for more details. The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 3 and 4 on page 10. ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a "1", the device is unable to verify that an erase or a byte/word program operation has been successfully performed. The device may also output a "1" on I/O5 if the system tries to program a "1" to a location that was previously programmed to a "0". Only an erase operation can change a "0" back to a "1". If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a "1", 6
AT49BV/LV320(T)/321(T)
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AT49BV/LV320(T)/321(T)
the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a "0" while the erase or program operation is still in progress. Please see "Status Bit Table" on page 11 for more details. VPP STATUS BIT: The AT49BV/LV32X(T) provides a status bit on I/O3, which provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a "1". Once the V PP status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status bit will output a "0". Please see "Status Bit Table" on page 11 for more details. SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector's usage as a write-protected region is optional to the user. At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see "Software Product Identification Entry/Exit" sections on page 25), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the system to interrupt a programming operation and then read data from a different byte/word within the memory. After the Program Suspend command is given, the device requires a maximum of 20 s to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other byte/word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same.
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PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see "Operating Modes" on page 18 (for hardware operation) or "Software Product Identification Entry/Exit" sections on page 25. The manufacturer and device codes are the same for both modes. 128-BIT PROTECTION REGISTER: The AT49BV/LV32X(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the "Command Definition in Hex" table on page 12. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the "Command Definition in Hex" table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don't cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the "Protection Register Addressing Table" on page 13 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation. RDY/BUSY: For the AT49BV/LV321(T), an open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. Please see "Status Bit Table" on page 11 for more details. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the AT49BV/LV32X(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e) Program inhibit: VPP is less than VILPP. (f) VPP power-on delay: once VPP has reached 1.65V, program and erase operations are inhibited for 100 ns. INPUT LEVELS: While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V. OUTPUT LEVELS: For the AT49BV/LV320(T), output high levels (VOH) are equal to V CCQ 0.2V (not VCC). For 2.65V - 3.6V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output levels, VCCQ must be regulated to 2.0V 10%, while VCC must be regulated to 2.65V - 3.0V (for minimum power).
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AT49BV/LV320(T)/321(T)
Figure 1. Data Polling Algorithm (Configuration Register = 00) Figure 2. Data Polling Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0 Addr = VA
Read I/O7 - I/O0
YES I/O7 = Data?
Toggle Bit = Toggle? NO
NO
YES
NO
I/O3, I/O5 = 1?
NO
I/O3, I/O5 = 1?
YES Read I/O7 - I/O0 Addr = VA
YES Read I/O7 - I/O0 Twice
I/O7 = Data?
YES
Toggle Bit = Toggle? YES
NO
NO Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode
Note: Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5.
Program/Erase Operation Not Successful, Write Product ID Exit Command
Program/Erase Operation Successful
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.
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Figure 3. Toggle Bit Algorithm (Configuration Register = 00)
Figure 4. Toggle Bit Algorithm (Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
Toggle Bit = Toggle? YES NO I/O3, I/O5 = 1?
NO
YES Read I/O7 - I/O0 Twice
YES Read I/O7 - I/O0 Twice
Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command
NO
Toggle Bit = Toggle? YES
NO
Program/Erase Operation Successful
Program/Erase Operation Not Successful, Write Product ID Exit Command
Program/Erase Operation Successful, Write Product ID Exit Command
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
Note:
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
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AT49BV/LV320(T)/321(T)
Status Bit Table
Status Bit I/O7 Configuration Register Programming Erasing Erase Suspended & Read Erasing Sector Erase Suspended & Read Non-erasing Sector Erase Suspended & Program Non-erasing Sector Notes: 00 I/O7 0 1 DATA I/O7 I/O7 01 0 0 1 DATA 0 I/O6 00/01 TOGGLE TOGGLE 1 DATA TOGGLE I/O5(1) 00/01 0 0 0 DATA 0 I/O3(2) 00/01 0 0 0 DATA 0 I/O2 00/01 1 TOGGLE TOGGLE DATA TOGGLE RDY/BUSY 00/01 0 0 1 1 0
1. I/O5 switches to a "1" when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a "1" when the VPP level is not high enough to successfully perform program and erase operations.
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Command Definition in Hex(1)
Command Sequence Read Chip Erase Sector Erase Byte/Word Program Enter Single Pulse Program Mode Single Pulse Byte/Word Program Sector Lockdown Erase/Program Suspend Erase/Program Resume Product ID Entry Product ID Exit(5) Product ID Exit(5) Program Protection Register Lock Protection Register - Block B Status of Block B Protection Set Configuration Register Bus Cycles 1 6 6 4 6 1 6 1 1 3 3 1 4 4 4 4 1st Bus Cycle Addr Addr 555 555 555 555 Addr 555 XXX XXX 555 555 XXX 555 555 555 555 Data DOUT AA AA AA AA DIN AA B0 30 AA AA F0 AA AA AA AA AAA AAA AAA AAA 55 55 55 55 555 555 555 555 C0 C0 90 D0 Addr 080 80 XXX DIN X0 DOUT(6) 00/01 (7) AAA AAA 55 55 555 555 90 F0 AAA(2) 55 555 80 555 AA AAA 55 SA(3)(4) 60 AAA(2) AAA AAA AAA 55 55 55 55 555 555 555 555 80 80 A0 80 555 555 Addr 555 AA AA DIN AA AAA 55 555 A0 AAA AAA 55 55 555 SA(3)(4) 10 30 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data Addr 4th Bus Cycle Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data
Notes:
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are don't care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11 are don't care in the word mode. Address A20 through A11 and A-1 are don't care in the byte mode. 2. Since A11 is a Don't Care, AAA can be replaced with 2AA. 3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 14 and 16 for details). 4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. Either one of the Product ID Exit commands can be used. 6. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed. 7. The default state (after power-up) of the configuration register is "00".
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and VPP with Respect to Ground ...................................-0.6V to +13.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT49BV/LV320(T)/321(T)
Protection Register Addressing Table
Word 0 1 2 3 4 5 6 7 Note: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0
All address lines not specified in the above table must be "0" when accessing the protection register, i.e., A20 - A8 = 0.
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1494H-FLASH-01/03
AT49BV/LV 320/321 - Sector Address Table
x8 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Bytes/Words) 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K Address Range (A20 - A-1) 000000 - 001FFF 002000 - 003FFF 004000 - 005FFF 006000 - 007FFF 008000 - 009FFF 00A000 - 00BFFF 00C000 - 00DFFF 00E000 - 00FFFF 010000 - 01FFFF 020000 - 02FFFF 030000 - 03FFFF 040000 - 04FFFF 050000 - 05FFFF 060000 - 06FFFF 070000 - 07FFFF 080000 - 08FFFF 090000 - 09FFFF 0A0000 - 0AFFFF 0B0000 - 0BFFFF 0C0000 - 0CFFFF 0D0000 - 0DFFFF 0E0000 - 0EFFFF 0F0000 - 0FFFFF 100000 - 10FFFF 110000 - 11FFFF 120000 - 12FFFF 130000 - 13FFFF 140000 - 14FFFF 150000 - 15FFFF 160000 - 16FFFF 170000 - 17FFFF 180000 - 18FFFF 190000 - 19FFFF 1A0000 - 1AFFFF 1B0000 - 1BFFFF 1C0000 - 1CFFFF x16 Address Range (A20 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF
14
AT49BV/LV320(T)/321(T)
1494H-FLASH-01/03
AT49BV/LV320(T)/321(T)
AT49BV/LV 320/321 - Sector Address Table (Continued)
x8 Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Size (Bytes/Words) 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K Address Range (A20 - A-1) 1D0000 - 1DFFFF 1E0000 - 1EFFFF 1F0000 - 1FFFFF 200000 - 20FFFF 210000 - 21FFFF 220000 - 22FFFF 230000 - 23FFFF 240000 - 24FFFF 250000 - 25FFFF 260000 - 26FFFF 270000 - 27FFFF 280000 - 28FFFF 290000 - 29FFFF 2A0000 - 2AFFFF 2B0000 - 2BFFFF 2C0000 - 2CFFFF 2D0000 - 2DFFFF 2E0000 - 2EFFFF 2F0000 - 2FFFFF 300000 - 30FFFF 310000 - 31FFFF 320000 - 32FFFF 330000 - 33FFFF 340000 - 34FFFF 350000 - 35FFFF 360000 - 36FFFF 370000 - 37FFFF 380000 - 38FFFF 390000 - 39FFFF 3A0000 - 3AFFFF 3B0000 - 3BFFFF 3C0000 - 3CFFFF 3D0000 - 3DFFFF 3E0000 - 3EFFFF 3F0000 - 3FFFFF x16 Address Range (A20 - A0) E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 -1F7FFF 1F8000 - 1FFFF
15
1494H-FLASH-01/03
AT49BV/LV 320T/321T - Sector Address Table
x8 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Size (Bytes/Words) 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K Address Range (A20 - A-1) 000000 - 00FFFF 010000 - 01FFFF 020000 - 02FFFF 030000 - 03FFFF 040000 - 04FFFF 050000 - 05FFFF 060000 - 06FFFF 070000 - 07FFFF 080000 - 08FFFF 090000 - 09FFFF 0A0000 - 0AFFFF 0B0000 - 0BFFFF 0C0000 - 0CFFFF 0D0000 - 0DFFFF 0E0000 - 0EFFFF 0F0000 - 0FFFFF 100000 - 10FFFF 110000 - 11FFFF 120000 - 12FFFF 130000 - 13FFFF 140000 - 14FFFF 150000 - 15FFFF 160000 - 16FFFF 170000 - 17FFFF 180000 - 18FFFF 190000 - 19FFFF 1A0000 - 1AFFFF 1B0000 - 1BFFFF 1C0000 - 1CFFFF 1D0000 - 1DFFFF IE0000 - IEFFFF 1F0000 - 1FFFFF 200000 - 20FFFF 210000 - 21FFFF 220000 - 22FFFF 230000 - 23FFFF 240000 - 24FFFF x16 Address Range (A20 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF
SA35 SA36
16
AT49BV/LV320(T)/321(T)
1494H-FLASH-01/03
AT49BV/LV320(T)/321(T)
AT49BV/LV 320T/321T - Sector Address Table (Continued)
x8 Sector SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Size (Bytes/Words) 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K Address Range (A20 - A-1) 250000 - 25FFFF 260000 - 26FFFF 270000 - 27FFFF 280000 - 28FFFF 290000 - 29FFFF 2A0000 - 2AFFFF 2B0000 - 2BFFFF 2C0000 - 2CFFFF 2D0000 - 2DFFFF 2E0000 - 2EFFFF 2F0000 - 2FFFFF 300000 - 30FFFF 310000 - 31FFFF 320000 - 32FFFF 330000 - 33FFFF 340000 - 34FFFF 350000 - 35FFFF 360000 - 36FFFF 370000 - 37FFFF 380000 - 38FFFF 390000 - 39FFFF 3A0000 - 3AFFFF 3B0000 - 3BFFFF 3C0000 - 3CFFFF 3D0000 - 3DFFFF 3E0000 - 3EFFFF 3F0000 - 3F1FFF 3F2000 - 3F3FFF 3F4000 - 3F5FFF 3F6000 - 3F7FFF 3F8000 - 3F9FFF 3FA000 - 3FBFFF 3FC000 - 3FDFFF 3FE000 - 3FFFFF x16 Address Range (A20 - A0) 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1F8FFF 1F9000 - 1F9FFF 1FA000 - 1FAFFF 1FB000 - 1FBFFF 1FC000 - 1FCFFF 1FD000 - 1FDFFF 1FE000 - 1FEFFF 1FF000 - 1FFFFF
17
1494H-FLASH-01/03
DC and AC Operating Range
AT49BV/LV32X(T)-85 Operating Temperature (Case) VCC Power Supply Ind. -40C - 85C 2.65V to 3.3V/3.0V to 3.6V AT49BV/LV32X(T)-90 -40C - 85C 2.65V to 3.3V/3.0V to 3.6V AT49BV/LV32X(T)-11 -40C - 85C 2.65V to 3.3V/3.0V to 3.6V
Operating Modes
Mode Read Program/Erase
(2)
CE VIL VIL VIH X
OE VIL VIH X
(1)
WE VIH VIL X VIH X X X X
RESET VIH VIH VIH VIH VIH VIH VIH VIL
VPP X VIHPP X X X VILPP(7) X X
(6)
Ai Ai Ai X
I/O DOUT DIN High-Z
Standby/Program Inhibit
X VIL X VIH X
Program Inhibit
X X
Output Disable Reset Product Identification Hardware
X X
High-Z X High-Z
VIL
VIL
VIH
VIH
A1 - A20 = V IL, A9 = V H(3), A0 = V IL A1 - A20 = VIL, A9 = V H(3), A0 = V IH A0 = VIL, A1 - A20 = VIL A0 = VIH, A1 - A20 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
VIH
Notes:
1. 2. 3. 4.
X can be VIL or VIH. Refer to AC programming waveforms on page 23. VH = 12.0V 0.5V. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C8H (x8)-AT49BV/LV32X; 00C8H (x16)-AT49BV/LV32X; C9H (x8)-AT49BV/LV32XT; 00C9H (x16)-AT49BV/LV32XT. 5. See details under "Software Product Identification Entry/Exit" on page 25. 6. VIHPP (min) = 1.65V; VIHPP (max) = 3.6V. 7. VILPP (max) = 0.8V.
18
AT49BV/LV320(T)/321(T)
1494H-FLASH-01/03
AT49BV/LV320(T)/321(T)
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ISB3 ICC
(1)(2)
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Standby Current TTL VCC Active Read Current VCC Programming Current VPP Input Load Current Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage
Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to V CC CE = 2.0V to VCC CE = 2.0V to VCC, V CC = 2.85V f = 5 MHz; IOUT = 0 mA
Min
Max 10 10 10 1 10 25 45 100 0.6
Units A A A mA A mA mA A V V
ICC1 IPP1 VIL VIH VOL1 VOL2 VOH1
2.0 IOL = 2.1 mA IOL = 1.0 mA IOH = -400 A VCCQ < 2.6V VCCQ 2.6V VCCQ < 2.6V VCCQ 2.6V VCCQ - 0.2 [AT49BV/LV320(T)] 2.4 [AT49BV/LV320(T)] 2.4 [AT49BV/LV321(T)] VCCQ - 0.1 [AT49BV/LV320(T)] 2.5 [AT49BV/LV320(T)] 2.5 [AT49BV/LV321(T)] IOH = -400 A IOH = -400 A IOH = -100 A 0.45 0.20
V V V V V V V V
Output High Voltage
VOH2
Output High Voltage
IOH = -100 A IOH = -100 A
Notes:
1. For 3.3V < VCC < 3.6V, ICC (max) = 30 mA. 2. In the erase mode, ICC is 65 mA.
19
1494H-FLASH-01/03
AC Read Characteristics
AT49BV/LV32X(T)-85 Symbol tRC tACC tCE
(1) (2)
AT49BV/LV32X(T)-90 Min Max 90 90 90 0 0 0 40 25
AT49BV/LV32X(T)-11 Min Max 110 110 110 0 0 0 45 30 Units ns ns ns ns ns ns 100 ns
Parameter Read Cycle Time Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first RESET to Output Delay
Min
Max 85 85 85
tOE
0 0 0
40 25
tDF(3)(4) tOH tRO
100
100
AC Read Waveforms(1)(2)(3)(4)
tRC ADDRESS ADDRESS VALID
CE
tCE OE tOE tDF tACC tOH
RESET HIGH Z
tRO OUTPUT VALID
OUTPUT
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
20
AT49BV/LV320(T)/321(T)
1494H-FLASH-01/03
AT49BV/LV320(T)/321(T)
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
Note:
This parameter is characterized and is not 100% tested.
21
1494H-FLASH-01/03
AC Byte/Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 50 50 0 35 Max Units ns ns ns ns ns ns ns ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
22
AT49BV/LV320(T)/321(T)
1494H-FLASH-01/03
AT49BV/LV320(T)/321(T)
Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tWC tRP tEC tSEC1 tSEC2 tES tPS Parameter Byte/Word Programming Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Write Cycle Time Reset Pulse Width Chip Erase Cycle Time Sector Erase Cycle Time (4K Word Sectors) Sector Erase Cycle Time (32K Word Sectors) Erase Suspend Time Program Suspend Time 0 50 50 0 50 35 85 500 13 60 200 90 300 15 20 Min Typ 15 Max 150 Units s ns ns ns ns ns ns ns ns seconds ms ms s s
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP tWPH tBP
WE
tAS tAH
555 AAA
tDH
555 ADDRESS 555
A0 - A20
tWC
tDS
AA 55 A0 INPUT DATA AA
DATA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP tWPH
WE
tAS tAH
555 AAA
tDH
555 555 AAA Note 2
A0-A20
tWC
tDS
AA 55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 Note 3 WORD 5
tEC
DATA
WORD 0
Notes:
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under "Command Definitions in Hex" on page 12.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
23
1494H-FLASH-01/03
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 20.
0
ns
Data Polling Waveforms
WE CE OE tDH I/O7 A0-A20 An tOEH tOE HIGH Z An An An An tWR
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 20.
(2)
Min 10 10
Typ
Max
Units ns ns ns
50 0
ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
24
AT49BV/LV320(T)/321(T)
1494H-FLASH-01/03
AT49BV/LV320(T)/321(T)
Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 555
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 555
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 90 TO ADDRESS 555
LOAD DATA 80 TO ADDRESS 555
LOAD DATA AA TO ADDRESS 555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
Software Product Identification Exit(1)(6)
LOAD DATA AA TO ADDRESS 555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 60 TO SECTOR ADDRESS
LOAD DATA 55 TO ADDRESS AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
PAUSE 200 s(2)
Notes:
LOAD DATA F0 TO ADDRESS 555
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A20 (Don't Care). 2. Sector Lockdown feature enabled.
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A20 (Don't Care). 2. A1 - A20 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH(x8); 001FH(x16) Device Code: C8 (x8) - AT49BV/LV32X; 00C8 (x16) - AT49BV/LV32X; C9H (x8) - AT49BV/LV32XT; 00C9H (x16) - AT49BV/LV32XT. 6. Either one of the Product ID Exit commands can be used.
25
1494H-FLASH-01/03
AT49BV320(T)/321(T) Ordering Information
tACC (ns) 85 90 110 85 90 110 85 90 110 85 90 110 ICC (mA) Active 25 25 25 25 25 25 25 25 25 25 25 25 Standby 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 Ordering Code AT49BV320-85TI AT49BV320-85UI AT49BV320-90TI AT49BV320-90UI AT49BV320-11TI AT49BV320-11UI AT49BV320T-85TI AT49BV320T-85UI AT49BV320T-90TI AT49BV320T-90UI AT49BV320T-11TI AT49BV320T-11UI AT49BV321-85CI AT49BV321-85TI AT49BV321-90CI AT49BV321-90TI AT49BV321-11CI AT49BV321-11TI AT49BV321T-85CI AT49BV321T-85TI AT49BV321T-90CI AT49BV321T-90TI AT49BV321T-11CI AT49BV321T-11TI Package 48T 46U 48T 46U 48T 46U 48T 46U 48T 46U 48T 46U 48C16 48T 48C16 48T 48C16 48T 48C16 48T 48C16 48T 48C16 48T Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C)
AT49LV320(T)/321(T) Ordering Information
tACC (ns) 90 90 90 90 ICC (mA) Active 25 25 25 25 Standby 0.01 0.01 0.01 0.01 Ordering Code AT49LV320-90TI AT49LV320-90UI AT49LV320T-90TI AT49LV320T-90UI AT49LV321-90CI AT49LV321-90TI AT49LV321T-90CI AT49LV321T-90TI Package 48T 46U 48T 46U 48C16 48T 48C16 48T Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C)
Package Type 48C16 48T 46U 48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 48-lead, Plastic Thin Small Outline Package (TSOP) 46-ball, Micro Ball Grid Array Package (BGA)
26
AT49BV/LV320(T)/321(T)
1494H-FLASH-01/03
AT49BV/LV320(T)/321(T)
Packaging Information
48C16 - CBGA
A1 Ball ID
E
D
Top View
A
2.00 REF
A1
E1 e
A1 Ball Corner
2.70 REF
Side View
A B C D
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
D1
MIN 7.90 - 10.90 - - 0.30
NOM 8.00 4.00 11.00 5.60 - - 0.80 BSC
MAX 8.10 - 11.10 - 1.20 -
NOTE
E F G H
E E1 D
e
6 5 4 3 2 1
D1 A A1 e b
Ob
Bottom View
-
0.40
-
6/12/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48C16, (Formerly 48C7), 48-ball (6 x 8 Array), 0.80 mm Pitch, 8.0 x 11.0 x 1.20 mm Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 48C16 REV. A
R
27
1494H-FLASH-01/03
48T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 11.90 0.50 NOM - - 1.00 20.00 18.40 12.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 12.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 48T REV. B
R
28
AT49BV/LV320(T)/321(T)
1494H-FLASH-01/03
AT49BV/LV320(T)/321(T)
46U - BGA
Dimensions in Millimeters (Inches) Controlling dimension: millimeters
7.70(0.303) 7.50(0.295)
10.50(0.413) 10.30(0.406)
0.20(0.008)MIN 5.25(0.207)
8 7 6 5 4 3 2 1
1.03(0.041)MAX
A B C D E F
3.75(0.148)
0.75(0.0295) TYP NON-ACCUMULATIVE
0.35(0.014) DIA TYP
06/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 46U, (Formerly 48U5), 46-ball (8 x 6 Array), 7.6 x 10.4 mm Body, 0.75 mm Pitch, Micro Ball Grid Array Package (BGA) DRAWING NO. 46U REV. B
R
29
1494H-FLASH-01/03
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 USA TEL 1(408) 441-0311 FAX 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759
Microcontrollers Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1494H-FLASH-01/03 /xM

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